1. Technical Field
The present application relates to integrated circuit interconnection technology.
2. Background Art
Integrated circuit (IC) chips or dies are typically interfaced with other circuits using a package that can be attached to a printed circuit board (PCB). One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. A BGA package has an array of solder ball pads located on a bottom external surface of a package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to the PCB.
An advanced type of BGA package is a wafer-level BGA package. Wafer-level BGA packages have several names in industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, the solder balls are mounted directly to the IC chip when the IC chip has not yet been singulated from its fabrication wafer. Wafer-level BGA packages can therefore be made very small, with high pin out, relative to other IC package types including traditional BGA packages.
A current move to tighter fabrication process technologies, such as 65 nm, with a continuing need to meet strict customer reliability requirements and ongoing cost pressures, is causing difficulties in implementing wafer-level BGA package technology. One challenge to expanding the use of wafer-level BGA packages is the large mismatch between the coefficient of thermal expansion (CTE) between a silicon die and a PCB. A silicon die typically expands very little when heated and a PCB tends to expand much more than the silicon die. Also the mechanical stiffness of the multi-layer PCB is much higher than that of a traditional substrate laminate. The difference in the amounts of thermal expansion can put stress on the solder joints between a wafer-level BGA package and a PCB when the components are thermally cycled, causing joint failure. Because the PCB is stiffer, thermal cycling-related joint failure will typically occur on the silicon die side of the joint. Joint reliability has made it difficult to mount wafer-level BGA packages with silicon dies larger in dimension than 6 mm (e.g., a 6 mm by 6 mm die) to a PCB, because larger dies correspond to a larger absolute thermal expansion mismatch, placing greater stress on the joints.